
print:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005b8 <.init>:
  4005b8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005bc:	910003fd 	mov	x29, sp
  4005c0:	94000042 	bl	4006c8 <__assert_fail@plt+0x58>
  4005c4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005c8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005d0 <strlen@plt-0x20>:
  4005d0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005d4:	90000090 	adrp	x16, 410000 <__assert_fail@plt+0xf990>
  4005d8:	f947fe11 	ldr	x17, [x16, #4088]
  4005dc:	913fe210 	add	x16, x16, #0xff8
  4005e0:	d61f0220 	br	x17
  4005e4:	d503201f 	nop
  4005e8:	d503201f 	nop
  4005ec:	d503201f 	nop

00000000004005f0 <strlen@plt>:
  4005f0:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  4005f4:	f9400211 	ldr	x17, [x16]
  4005f8:	91000210 	add	x16, x16, #0x0
  4005fc:	d61f0220 	br	x17

0000000000400600 <malloc@plt>:
  400600:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400604:	f9400611 	ldr	x17, [x16, #8]
  400608:	91002210 	add	x16, x16, #0x8
  40060c:	d61f0220 	br	x17

0000000000400610 <__libc_start_main@plt>:
  400610:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400614:	f9400a11 	ldr	x17, [x16, #16]
  400618:	91004210 	add	x16, x16, #0x10
  40061c:	d61f0220 	br	x17

0000000000400620 <memset@plt>:
  400620:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400624:	f9400e11 	ldr	x17, [x16, #24]
  400628:	91006210 	add	x16, x16, #0x18
  40062c:	d61f0220 	br	x17

0000000000400630 <__gmon_start__@plt>:
  400630:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400634:	f9401211 	ldr	x17, [x16, #32]
  400638:	91008210 	add	x16, x16, #0x20
  40063c:	d61f0220 	br	x17

0000000000400640 <abort@plt>:
  400640:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400644:	f9401611 	ldr	x17, [x16, #40]
  400648:	9100a210 	add	x16, x16, #0x28
  40064c:	d61f0220 	br	x17

0000000000400650 <puts@plt>:
  400650:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400654:	f9401a11 	ldr	x17, [x16, #48]
  400658:	9100c210 	add	x16, x16, #0x30
  40065c:	d61f0220 	br	x17

0000000000400660 <printf@plt>:
  400660:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400664:	f9401e11 	ldr	x17, [x16, #56]
  400668:	9100e210 	add	x16, x16, #0x38
  40066c:	d61f0220 	br	x17

0000000000400670 <__assert_fail@plt>:
  400670:	b0000090 	adrp	x16, 411000 <__assert_fail@plt+0x10990>
  400674:	f9402211 	ldr	x17, [x16, #64]
  400678:	91010210 	add	x16, x16, #0x40
  40067c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400680 <.text>:
  400680:	d280001d 	mov	x29, #0x0                   	// #0
  400684:	d280001e 	mov	x30, #0x0                   	// #0
  400688:	aa0003e5 	mov	x5, x0
  40068c:	f94003e1 	ldr	x1, [sp]
  400690:	910023e2 	add	x2, sp, #0x8
  400694:	910003e6 	mov	x6, sp
  400698:	580000c0 	ldr	x0, 4006b0 <__assert_fail@plt+0x40>
  40069c:	580000e3 	ldr	x3, 4006b8 <__assert_fail@plt+0x48>
  4006a0:	58000104 	ldr	x4, 4006c0 <__assert_fail@plt+0x50>
  4006a4:	97ffffdb 	bl	400610 <__libc_start_main@plt>
  4006a8:	97ffffe6 	bl	400640 <abort@plt>
  4006ac:	00000000 	.inst	0x00000000 ; undefined
  4006b0:	0040080c 	.inst	0x0040080c ; undefined
  4006b4:	00000000 	.inst	0x00000000 ; undefined
  4006b8:	00400918 	.inst	0x00400918 ; undefined
  4006bc:	00000000 	.inst	0x00000000 ; undefined
  4006c0:	00400998 	.inst	0x00400998 ; undefined
  4006c4:	00000000 	.inst	0x00000000 ; undefined
  4006c8:	90000080 	adrp	x0, 410000 <__assert_fail@plt+0xf990>
  4006cc:	f947f000 	ldr	x0, [x0, #4064]
  4006d0:	b4000040 	cbz	x0, 4006d8 <__assert_fail@plt+0x68>
  4006d4:	17ffffd7 	b	400630 <__gmon_start__@plt>
  4006d8:	d65f03c0 	ret
  4006dc:	00000000 	.inst	0x00000000 ; undefined
  4006e0:	b0000080 	adrp	x0, 411000 <__assert_fail@plt+0x10990>
  4006e4:	91016000 	add	x0, x0, #0x58
  4006e8:	b0000081 	adrp	x1, 411000 <__assert_fail@plt+0x10990>
  4006ec:	91016021 	add	x1, x1, #0x58
  4006f0:	eb00003f 	cmp	x1, x0
  4006f4:	540000a0 	b.eq	400708 <__assert_fail@plt+0x98>  // b.none
  4006f8:	90000001 	adrp	x1, 400000 <strlen@plt-0x5f0>
  4006fc:	f944dc21 	ldr	x1, [x1, #2488]
  400700:	b4000041 	cbz	x1, 400708 <__assert_fail@plt+0x98>
  400704:	d61f0020 	br	x1
  400708:	d65f03c0 	ret
  40070c:	d503201f 	nop
  400710:	b0000080 	adrp	x0, 411000 <__assert_fail@plt+0x10990>
  400714:	91016000 	add	x0, x0, #0x58
  400718:	b0000081 	adrp	x1, 411000 <__assert_fail@plt+0x10990>
  40071c:	91016021 	add	x1, x1, #0x58
  400720:	cb000021 	sub	x1, x1, x0
  400724:	9343fc21 	asr	x1, x1, #3
  400728:	8b41fc21 	add	x1, x1, x1, lsr #63
  40072c:	9341fc21 	asr	x1, x1, #1
  400730:	b40000a1 	cbz	x1, 400744 <__assert_fail@plt+0xd4>
  400734:	90000002 	adrp	x2, 400000 <strlen@plt-0x5f0>
  400738:	f944e042 	ldr	x2, [x2, #2496]
  40073c:	b4000042 	cbz	x2, 400744 <__assert_fail@plt+0xd4>
  400740:	d61f0040 	br	x2
  400744:	d65f03c0 	ret
  400748:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40074c:	910003fd 	mov	x29, sp
  400750:	f9000bf3 	str	x19, [sp, #16]
  400754:	b0000093 	adrp	x19, 411000 <__assert_fail@plt+0x10990>
  400758:	39416260 	ldrb	w0, [x19, #88]
  40075c:	35000080 	cbnz	w0, 40076c <__assert_fail@plt+0xfc>
  400760:	97ffffe0 	bl	4006e0 <__assert_fail@plt+0x70>
  400764:	52800020 	mov	w0, #0x1                   	// #1
  400768:	39016260 	strb	w0, [x19, #88]
  40076c:	f9400bf3 	ldr	x19, [sp, #16]
  400770:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400774:	d65f03c0 	ret
  400778:	17ffffe6 	b	400710 <__assert_fail@plt+0xa0>
  40077c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400780:	910003fd 	mov	x29, sp
  400784:	f9000fa0 	str	x0, [x29, #24]
  400788:	f9000ba1 	str	x1, [x29, #16]
  40078c:	f9400fa0 	ldr	x0, [x29, #24]
  400790:	f100001f 	cmp	x0, #0x0
  400794:	54000080 	b.eq	4007a4 <__assert_fail@plt+0x134>  // b.none
  400798:	f9400ba0 	ldr	x0, [x29, #16]
  40079c:	f100001f 	cmp	x0, #0x0
  4007a0:	54000141 	b.ne	4007c8 <__assert_fail@plt+0x158>  // b.any
  4007a4:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  4007a8:	91296002 	add	x2, x0, #0xa58
  4007ac:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  4007b0:	91272001 	add	x1, x0, #0x9c8
  4007b4:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  4007b8:	91274000 	add	x0, x0, #0x9d0
  4007bc:	aa0203e3 	mov	x3, x2
  4007c0:	52800102 	mov	w2, #0x8                   	// #8
  4007c4:	97ffffab 	bl	400670 <__assert_fail@plt>
  4007c8:	f9400fa0 	ldr	x0, [x29, #24]
  4007cc:	f90017a0 	str	x0, [x29, #40]
  4007d0:	d503201f 	nop
  4007d4:	f9400ba1 	ldr	x1, [x29, #16]
  4007d8:	91000420 	add	x0, x1, #0x1
  4007dc:	f9000ba0 	str	x0, [x29, #16]
  4007e0:	f9400fa0 	ldr	x0, [x29, #24]
  4007e4:	91000402 	add	x2, x0, #0x1
  4007e8:	f9000fa2 	str	x2, [x29, #24]
  4007ec:	39400021 	ldrb	w1, [x1]
  4007f0:	39000001 	strb	w1, [x0]
  4007f4:	39400000 	ldrb	w0, [x0]
  4007f8:	7100001f 	cmp	w0, #0x0
  4007fc:	54fffec1 	b.ne	4007d4 <__assert_fail@plt+0x164>  // b.any
  400800:	f94017a0 	ldr	x0, [x29, #40]
  400804:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400808:	d65f03c0 	ret
  40080c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400810:	910003fd 	mov	x29, sp
  400814:	f9000bf3 	str	x19, [sp, #16]
  400818:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  40081c:	91294001 	add	x1, x0, #0xa50
  400820:	910083a0 	add	x0, x29, #0x20
  400824:	b9400022 	ldr	w2, [x1]
  400828:	b9000002 	str	w2, [x0]
  40082c:	b8401021 	ldur	w1, [x1, #1]
  400830:	b8001001 	stur	w1, [x0, #1]
  400834:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  400838:	9127c000 	add	x0, x0, #0x9f0
  40083c:	f9001fa0 	str	x0, [x29, #56]
  400840:	d2800280 	mov	x0, #0x14                  	// #20
  400844:	97ffff6f 	bl	400600 <malloc@plt>
  400848:	f90017a0 	str	x0, [x29, #40]
  40084c:	d2800282 	mov	x2, #0x14                  	// #20
  400850:	52800001 	mov	w1, #0x0                   	// #0
  400854:	f94017a0 	ldr	x0, [x29, #40]
  400858:	97ffff72 	bl	400620 <memset@plt>
  40085c:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  400860:	9127e000 	add	x0, x0, #0x9f8
  400864:	f90017a0 	str	x0, [x29, #40]
  400868:	f9401fa0 	ldr	x0, [x29, #56]
  40086c:	97ffff61 	bl	4005f0 <strlen@plt>
  400870:	aa0003f3 	mov	x19, x0
  400874:	910083a0 	add	x0, x29, #0x20
  400878:	97ffff5e 	bl	4005f0 <strlen@plt>
  40087c:	aa0003e1 	mov	x1, x0
  400880:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  400884:	9128a000 	add	x0, x0, #0xa28
  400888:	d28000a5 	mov	x5, #0x5                   	// #5
  40088c:	aa0103e4 	mov	x4, x1
  400890:	d2800103 	mov	x3, #0x8                   	// #8
  400894:	aa1303e2 	mov	x2, x19
  400898:	f9401fa1 	ldr	x1, [x29, #56]
  40089c:	97ffff71 	bl	400660 <printf@plt>
  4008a0:	f94017a0 	ldr	x0, [x29, #40]
  4008a4:	97ffff53 	bl	4005f0 <strlen@plt>
  4008a8:	aa0003e1 	mov	x1, x0
  4008ac:	90000000 	adrp	x0, 400000 <strlen@plt-0x5f0>
  4008b0:	91290000 	add	x0, x0, #0xa40
  4008b4:	d2800103 	mov	x3, #0x8                   	// #8
  4008b8:	aa0103e2 	mov	x2, x1
  4008bc:	f94017a1 	ldr	x1, [x29, #40]
  4008c0:	97ffff68 	bl	400660 <printf@plt>
  4008c4:	b90037bf 	str	wzr, [x29, #52]
  4008c8:	1400000b 	b	4008f4 <__assert_fail@plt+0x284>
  4008cc:	f9401fa0 	ldr	x0, [x29, #56]
  4008d0:	91000401 	add	x1, x0, #0x1
  4008d4:	f9001fa1 	str	x1, [x29, #56]
  4008d8:	39400002 	ldrb	w2, [x0]
  4008dc:	b98037a0 	ldrsw	x0, [x29, #52]
  4008e0:	910083a1 	add	x1, x29, #0x20
  4008e4:	38206822 	strb	w2, [x1, x0]
  4008e8:	b94037a0 	ldr	w0, [x29, #52]
  4008ec:	11000400 	add	w0, w0, #0x1
  4008f0:	b90037a0 	str	w0, [x29, #52]
  4008f4:	b94037a0 	ldr	w0, [x29, #52]
  4008f8:	7100081f 	cmp	w0, #0x2
  4008fc:	54fffe8d 	b.le	4008cc <__assert_fail@plt+0x25c>
  400900:	910083a0 	add	x0, x29, #0x20
  400904:	97ffff53 	bl	400650 <puts@plt>
  400908:	52800000 	mov	w0, #0x0                   	// #0
  40090c:	f9400bf3 	ldr	x19, [sp, #16]
  400910:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400914:	d65f03c0 	ret
  400918:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  40091c:	910003fd 	mov	x29, sp
  400920:	a901d7f4 	stp	x20, x21, [sp, #24]
  400924:	90000094 	adrp	x20, 410000 <__assert_fail@plt+0xf990>
  400928:	90000095 	adrp	x21, 410000 <__assert_fail@plt+0xf990>
  40092c:	91374294 	add	x20, x20, #0xdd0
  400930:	913722b5 	add	x21, x21, #0xdc8
  400934:	a902dff6 	stp	x22, x23, [sp, #40]
  400938:	cb150294 	sub	x20, x20, x21
  40093c:	f9001ff8 	str	x24, [sp, #56]
  400940:	2a0003f6 	mov	w22, w0
  400944:	aa0103f7 	mov	x23, x1
  400948:	9343fe94 	asr	x20, x20, #3
  40094c:	aa0203f8 	mov	x24, x2
  400950:	97ffff1a 	bl	4005b8 <strlen@plt-0x38>
  400954:	b4000194 	cbz	x20, 400984 <__assert_fail@plt+0x314>
  400958:	f9000bb3 	str	x19, [x29, #16]
  40095c:	d2800013 	mov	x19, #0x0                   	// #0
  400960:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400964:	aa1803e2 	mov	x2, x24
  400968:	aa1703e1 	mov	x1, x23
  40096c:	2a1603e0 	mov	w0, w22
  400970:	91000673 	add	x19, x19, #0x1
  400974:	d63f0060 	blr	x3
  400978:	eb13029f 	cmp	x20, x19
  40097c:	54ffff21 	b.ne	400960 <__assert_fail@plt+0x2f0>  // b.any
  400980:	f9400bb3 	ldr	x19, [x29, #16]
  400984:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400988:	a942dff6 	ldp	x22, x23, [sp, #40]
  40098c:	f9401ff8 	ldr	x24, [sp, #56]
  400990:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400994:	d65f03c0 	ret
  400998:	d65f03c0 	ret

Disassembly of section .fini:

000000000040099c <.fini>:
  40099c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4009a0:	910003fd 	mov	x29, sp
  4009a4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4009a8:	d65f03c0 	ret
